1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit provided with an output circuit that outputs a signal to the outside.
2. Description of the Related Art
With electronic equipment, such as computers, signals are transferred through a common bus line. FIG. 1 is a circuit diagram of a typical connection in a bus line application. To a bus line 500, the signal from each of two tristate buffers 501 and 502 serving as the output circuits of different semiconductor integrated circuits is outputted. When the enable signals EN1 and EN2 are activated, both of the tristate buffers output the signals corresponding to the input signals IN1 and IN2 onto the bus line 500, whereas when the enable signals EN1, EN2 are inactivated, the outputs are brought into a high impedance state. Here, it is assumed that separate power-supply voltages Vcc1 and Vcc2 differing in value are supplied to the tristate buffers 501 and 502, respectively. In one tristate buffer 501, a parasitic diode 503 is inserted between the power supply and the output node with the polarity as shown in the figure.
When CMOS tristate buffers are used as the two tristate buffers, a p-channel MOS transistor 511 and an n-channel MOS transistor 512 are provided in the output stage as shown in FIG. 2. The gate driving signal supplied to the p-channel MOS transistor 511 is formed by a NAND gate 514 to which an input signal IN (IN1 or IN2) and the output of an inverter 513 that inverts an enable signal EN (EN1 or EN2) are supplied. The gate driving signal supplied to the n-channel MOS transistor 512 is formed by a NOR gate to which the enable signal EN and the input signal IN are supplied. The p-type drain diffused layer of the p-channel MOS transistor 511 and the n-type drain diffused layer of the n-channel MOS transistor 512 are connected to an output node 516, thus forming a parasitic p-n junction diode 517 between the output node 516 and the back gate of the p-channel MOS transistor 511. The diode 517 is the parasitic diode 503 in FIG. 1.
Consider a case where in FIG. 1, one tristate buffer 502 outputs a high level signal and the other tristate buffer 501 is in the high impedance state at its output. In this case, if both of the power supply voltages Vcc1 and Vcc2 and the built-in voltage Vf of the p-n junction between the drain diffused layer and back gate of the p-channel MOS transistor satisfy Vcc1&lt;Vcc2-Vf, the diode 503 will be brought into the forward bias state, permitting current I to flow from power supply Vcc2 to power supply Vcc1 via that diode as shown in FIG. 1.
To solve this problem, the applicant of the present invention has disclosed an output circuit improved so as to prevent such a current from flowing, in Japanese Patent Application No. 6-19432. The output stage of the output circuit related to the application is provided with a first p-channel MOS transistor for high-voltage output that has a source, a drain, a gate, and a back gate, with the source being potentially isolated from the back gate, an n-channel MOS transistor for low-voltage output, and a second p-channel MOS transistor that is inserted between the back gate and the gate of the first p-channel MOS transistor and functions as a switch for switching the back gate voltage of the first p-channel MOS transistor to the gate side. FIG. 3 shows a concrete circuit configuration of part of the output stage.
Between a power supply voltage Vcc and a signal output terminal IO, the current path between the source and drain of a first p-channel MOS transistor 601 for high voltage output is inserted, with the back gate (e.g., an n-well) of the transistor 601 being unconnected to the power supply voltage Vcc. Between the terminal IO and the ground voltage, the current path between the source and drain of an n-channel MOS transistor 602 for low voltage output is inserted. Between the back gate of the transistor 601 and the gate of the transistor 601, the current path between the source and drain of the p-channel MOS transistor 603 functioning as a switch is inserted. The transistor 603 has its gate connected to the ground voltage and is in the on state.
With the circuit constructed as shown in FIG. 3, because the source and back gate of the p-channel MOS transistor 601 are isolated potentially from each other, even if a higher voltage than the source voltage Vcc is applied to the terminal IO, current will not flow toward the source (the node of the power supply Vcc) via a p-n junction diode 604 existing parasitically between the drain (p-type diffused layer) and back gate (n-well) of the p-channel MOS transistor 601.
The diode 604 causes a voltage lower than the voltage of the terminal IO by the p-n junction built-in voltage of the diode 604 to appear at the back gate. This voltage is supplied to the gate of the transistor 601 via the transistor 603 functioning as a switch. As a result, the gate of the transistor 601 does not go to the floating state potentially. The value of the p-n built-in voltage is determined by the amount of a leakage current flowing from the node of the back gate to the ground. Since the leakage current is made small sufficiently, however, the built-in voltage is sufficiently smaller than the absolute value of the threshold voltage of the transistor 601, bringing the transistor 601 into the off state. Consequently, current will flow through neither the transistor 601 nor the diode 604 from the terminal IO to Vcc node.
As device miniaturization has progressed further, however, a new problem has arisen as follows. With the progress of device miniaturization, the breakdown voltage of the MOS transistor tends to get lower. At present, processing techniques recommending 5-V power-supply voltage operation (hereinafter, referred to as 5-V processing) are being replaced with processing techniques recommending 3.3-V power-supply voltage operation (hereinafter, referred to as 3.3-V processing). With this backdrop, the number of hybrid 5-V and 3.3-V systems is increasing.
In the case of devices manufactured by the 5-V processing, use of the circuit techniques in the previous application makes it unnecessary to consider the breakdown problem. When the circuit techniques in the previous application are applied to the devices manufactured by the 3.3-V processing, however, a 5-V signal can be applied between the gate and drain or source of the MOS transistor unless a suitable measure is taken, introducing the danger of degrading the reliability of the transistor. For instance, in the circuit of FIG. 3, since the gate of the transistor 603 is connected to the ground voltage, the potential difference between the gate and the terminal IO is 5V when a voltage of 5V is applied to the terminal IO, introducing the danger of impairing the reliability of the transistor 603.
The problem with the previous application will be explained using a concrete circuit. FIG. 4 shows the configuration of an embodiment of the output circuit in the previous application. The basic configuration of the output circuit is such that the output stage is composed of a p-channel and n-channel MOS transistors and the stage that generates driving signals for driving the gates of both of the transistors is composed of a NAND circuit, a NAND gate, a NOR gate, and an inverter.
The drains of the p-channel MOS transistor (hereinafter, referred to as the PMOS transistor) P1 and the n-channel MOS transistor (hereinafter, referred to as the NMOS transistor) N1 are both connected to the terminal IO. The source of the PMOS transistor P1 is connected to the power-supply voltage Vcc and the source of the NMOS transistor N1 is connected to the ground voltage.
When a PMOS transistor P7 is on, PMOS transistors P2 and P3 and NMOS transistors N2 and N3 constitute a NAND circuit that generates a gate driving signal for the PMOS transistor P1. Specifically, the source of PMOS transistor P2 is connected to that of PMOS transistor P3 to form a common source. The drain of PMOS transistor P2 is connected to that of PMOS transistor P3 to form a common drain, which is connected to the gate of the PMOS transistor P1. Between the gate of PMOS transistor P1 and the ground voltage, the current path between the drain and source of NMOS transistor N2 and the current path between the drain and source of NMOS transistor N3 are connected in series. The gate of PMOS transistor P2 is connected to the gate of NMOS transistor N3 to form a common gate, to which an input signal IN is supplied. The gate of PMOS transistor P3 is connected to the gate of NMOS transistor N2 to form a common gate, to which an output enable signal /OE is supplied via an inverter INV1.
A NOR gate NOR1 is supplied with the output enable signal /OE and the input signal IN and generates a gate driving signal for the NMOS transistor N1.
The output of the inverter INV1 is supplied to a NAND gate NAND1 via an inverter INV2. The NAND gate NAND1 is supplied with the signal /OE. The inverters INV1 and INV2 and NAND gate NAND1 constitute a delay circuit DL that delays the signal /OE for a specified period of time.
To the back gate of the PMOS transistor P1, the drain and back gate of PMOS transistor P4 are connected. The PMOS transistor P4 has its source connected to the power-supply voltage Vcc and its gate connected to the terminal IO. The PMOS transistor P4 is on when the terminal IO is at the low level, thereby supplying the power-supply voltage Vcc to the back gate of PMOS transistor P1.
To the back gate of the PMOS transistor P1, the drain and back gate of the PMOS transistor P5 are connected. The PMOS transistor P5 has its source connected to the terminal IO and its gate connected to the power-supply voltage Vcc. The PMOS transistor P5 is on when the voltage at the terminal IO is more than a specified value higher than the power-supply voltage Vcc, thereby supplying the voltage at the terminal IO to the back gate of the PMOS transistor P1.
Between the back gate and gate of the PMOS transistor P1, the current path between the source and drain of PMOS transistor P6 is connected. The PMOS transistor P6 corresponds to the transistor 603 in FIG. 3. The output of the NAND gate NAND1 provides on/off control of the PMOS transistor P6. When being turned on, the PMOS transistor P6 allows the voltage at the back gate of PMOS transistor P1 to be outputted to the gate side.
To the common source of the PMOS transistors P2 and P3, the drain of the PMOS transistor P7 is connected. The source of the PMOS transistor P7 is connected to the power-supply voltage Vcc.
In response to the output of the NAND gate NAND1, a PMOS transistor P8 and an NMOS transistor N4 generate a control signal according to the ground voltage and the voltage at the terminal IO. The source of PMOS transistor P8 is connected to the terminal IO. The drain of PMOS transistor P8 is connected to that of NMOS transistor N4 to form a common drain and the gate of PMOS transistor P8 is connected to that of NMOS transistor N4 to form a common gate. The source of NMOS transistor N4 is connected to the ground voltage.
The current path between the source and drain of a PMOS transistor P9 is connected between the power-supply voltage Vcc and the back gate of the PMOS transistor P1. The signal at the common drain of the PMOS transistor P8 and NMOS transistor N4 is supplied to the gates of both of the PMOS transistors P7 and P9.
With the circuit thus constructed, when the output enable signal /OE is at Vcc, or at the high level, the signal output terminal IO is in a high impedance state. At this time, the gates of the NMOS transistors N1, N2, and N4 are at the ground voltage. Since the output of the NAND gate NAND1 is at the ground voltage, the gates of PMOS transistors P6 and P8 are at the ground voltage.
Here, it is assumed that a voltage higher than Vcc (3.3V), for example, 5V, is applied to the terminal IO. In this case, a voltage difference of 5V is consequently applied between the gates and drains of the NMOS transistor N1, N2, N4, introducing the danger of degrading the reliability of these NMOS transistors. A potential difference of 5V is also applied between the gates and sources of the PMOS transistors P6 and P8, introducing the danger of degrading the reliability of these PMOS transistors. In addition, the potential of 5V is applied to the node at the gate of the PMOS transistor P1 via PMOS transistor P6. Since the gate voltage of the PMOS transistor P3 is the ground voltage, a potential difference of 5V is also applied between the gate and source of the PMOS transistor P3. When the input signal IN is set at the ground voltage, the same problem arises on the PMOS transistor P2 side.
FIG. 5 shows the configuration of another embodiment of the output circuit in the previous application. The circuit of FIG. 5 differs from the circuit of FIG. 4 in that a NAND gate NAND2 is provided in place of the NAND circuit composed of the PMOS transistors P2 and P3 and NMOS transistors N2 and N3 and the PMOS transistor P7 supplying the Vcc potential to the NAND circuit and in that a CMOS transfer gate composed of a PMOS transistor P10 and an NMOS transistor N5 is provided between the output node of the NAND gate NAND2 and the gate of the PMOS transistor P1. The gate of the PMOS transistor P10 constituting the transfer gate is connected to the common drain of the PMOS transistor P8 and NMOS transistor N4. The gate of NMOS transistor N5 is connected to the output node of the NAND gate NAND1.
With the circuit thus constructed, when the output enable signal /OE is at Vcc, or at the high level, the signal output terminal IO is in the high impedance state. At this time, the gates of the NMOS transistors N1, N4, and N5 are at the ground voltage. Since the output of the NAND gate NAND1 is at the ground voltage, the gates of the PMOS transistors P6 and P8 are at the ground voltage.
Here, it is assumed that a voltage higher than Vcc (3.3V), for example 5V, is applied to the terminal IO. In this case, a potential difference of 5V is consequently applied between the gates and drains of the NMOS transistors N1, N4, and N5, introducing the danger of degrading the reliability of these NMOS transistors. A potential difference of 5V is also applied between the gates and sources of the PMOS transistors P6 and P8, introducing the danger of degrading the reliability of these PMOS transistors.
As has been explained by reference to FIGS. 4 and 5, the circuit in the previous application causes the problem that a potential difference exceeding the breakdown voltage is applied between the gate and drain of the transistor, thus impairing the reliability, when a higher voltage (e.g., 5V) signal is applied to the output terminal of a circuit produced by low-breakdown voltage processing, such as 3.3-V processing.